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Nombre de documents trouvés : 44 documents
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A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects
Bosio A., Girard P., Pravossoudovitch S., Virazel A.
IEEE Transactions on Computers N/A (2009) 001-013 [lirmm-00433461 − version 1]
A Logic Diagnosis Approach for Sequential Circuits
Benabboud Y., Bosio A., Dilillo L., Girard P., Pravossoudovitch S., Virazel A., Bouzaida L., Izaute I.
IEEE European Test Symposium'09, Ph. D. Forum, Espagne [lirmm-00433792 − version 1]
Comprehensive Bridging Fault Diagnosis based on the SLAT Paradigm
Benabboud Y., Bosio A., Dilillo L., Girard P., Virazel A., Pravossoudovitch S., Bouzaida L., Izaute I.
DDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, [lirmm-00371198 − version 1]
An Efficient Fault Simulation Technique for Transition Faults in Non-Scan Sequential Circuits
Bosio A., Bernardi P., Girard P., Pravossoudovitch S., Sonza Reorda M.
DDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, [lirmm-00371197 − version 1]
A Fault-Simulation-Based Approach for Logic Diagnosis
Benabboud Y., Bosio A., Girard P., Pravossoudovitch S., Virazel A., Dilillo L.
DTIS'09: 4th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, [lirmm-00371377 − version 1]
A Case Study on Logic Diagnosis for System-on-Chip
Benabboud Y., Bosio A., Girard P., Pravossoudovitch S., Virazel A., Bouzaida L., Izaute I.
ISQED'09: IEEE 10th International Symposium on Quality Electronic Design, (2009) [lirmm-00370646 − version 1]
Trade-off Between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing Schemes
Wu F., Dilillo L., Bosio A., Girard P., Pravossoudovitch S., Virazel A., Wen X.
Impact of Low-Power Design on Test and Reliability, Espagne [lirmm-00435005 − version 1]
SRAM Core-cell Quality Metrics
Alves Fonseca R., Dilillo L., Bosio A., Girard P., Pravossoudovitch S., Virazel A., Badereddine N.
GDR SOC SIP, France [lirmm-00434962 − version 1]
Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes
Wu F., Dilillo L., Bosio A., Girard P., Pravossoudovitch S., Virazel A., Wen X.
GDR SOC SIP, France [lirmm-00434959 − version 1]
SoC Yield Improvement for Future Nanoscale Technologies
Vial J., Virazel A., Bosio A., Dilillo L., Girard P., Landrault C., Pravossoudovitch S.
European Test Symposium. PhD Forum, Espagne [lirmm-00433798 − version 1]
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