RISC-V has emerged as a versatile open-source instruction set architecture, enabling extensible microarchitectures, custom accelerators, and domain-specific processors. Its openness facilitates innovation in testability, safety, and security for safety-critical and security-sensitive applications. This survey provides a comprehensive review of recent research in RISC-V verification and protection mechanisms. We analyze AI-assisted test generation, statistical fault injection frameworks, systemlevel testing, design-for-test architectures, and hardware-software co-verification methods. In the safety domain, we discuss temporal isolation, performance monitoring, debug support, and fault containment strategies. Security mechanisms, including trusted execution environments, memory protection, cryptographic ISA extensions, post-quantum acceleration, and secure debug practices, are evaluated. Open challenges in scalable test coverage, AI-enabled certification, side-channel resilience, and lifecycle management are highlighted. Finally, we outline future research directions that leverage RISC-V's modularity and openness to enable trustworthy computing systems in automotive, aerospace, telecommunications, and edge computing domains.