Memory Heavy ions Switches VLSI Multiple cell upset MCU SER MRAM Core-cell Integrated circuit modeling Delays Logic testing Accelerometers Voltage Through-silicon vias Memory test Automatic test pattern generation Heating SRAM Reliability Integrated circuit design Cryptographie Modeling Single Event Upset Radiation Embedded systems Hardware security Microprocessors DPA Analytical models Silicon SEU Monitoring Cross-section Hardware Calibration BIST Countermeasures Random access memory Power demand Memory device Circuit faults Fault attacks Field programmable gate arrays Flip-flops Cross section CMOS integrated circuits Estimation Libraries Memories Neutrons Cryptography Fiabilité Magnetic tunneling Clocks Simulation DFT Neutron FPGA Test Design space exploration Logic gates Resistive-open defects Sensors RSA Security MEMS Fault modeling CMOS Testing Spintronics Thermal sensor Integrated circuit testing Circuit testing AES Low-power design Delay testing Testability Variability Soft errors Noise Atmospheric neutrons Electromagnetic Analysis Fault injection Transient faults Design Accelerometer Computer architecture Fault tolerance Hardware Trojan Transistors Crosstalk Power consumption Diagnostic Failure analysis Integrated circuit interconnections ATPG Single event upset SEU Low power Robustness SoC