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 SEU testing of a novel hardened register implemented using standard CMOS technology Thierry Monnier 285874-0 Fernand-Michel Roche 898301-0 J. Cosculluela 110491-0 Raoul Velazco a357d58216f70244bc3700b2c4d47ab8 univ-grenoble-alpes.fr raoul-velazco 737006 29171-737006 Lucie Torella 66185431a413e8ba3d3ee290a2814345 univ-grenoble-alpes.fr 2005-08-26 14:08:25 2026-03-26 11:44:10 2005-08-26 14:08:25 1999 contributor Lucie Torella 66185431a413e8ba3d3ee290a2814345 univ-grenoble-alpes.fr CCSD hal-00008234 https://hal.science/hal-00008234 monnier:hal-00008234 <i>IEEE Transactions on Nuclear Science</i>, 1999, 46 (6), pp.1440-1444. <a target="_blank" href="https://dx.doi.org/10.1109/23.819105">&#x27E8;10.1109/23.819105&#x27E9;</a> IEEE Transactions on Nuclear Science, 1999, 46 (6), pp.1440-1444. &#x27E8;10.1109/23.819105&#x27E9; HAL Grenoble Alpes CNRS - Centre national de la recherche scientifique Université Joseph Fourier - Grenoble I Institut polytechnique de Grenoble Techniques of Informatics and Microelectronics for integrated systems Architecture SysMic Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier MIC Département Microélectronique Mathématiques, Informatique, Physique et Systèmes Université de Montpellier Université de Montpellier (2015-2021) TEST-UGA International No Yes SEU testing of a novel hardened register implemented using standard CMOS technology Thierry Monnier 285874-0 Fernand-Michel Roche 898301-0 J. Cosculluela 110491-0 Raoul Velazco a357d58216f70244bc3700b2c4d47ab8 univ-grenoble-alpes.fr raoul-velazco 737006 29171-737006 5388 0018-9499 1558-1578 IEEE Transactions on Nuclear Science Institute of Electrical and Electronics Engineers 46 6 1440-1444 1999 10.1109/23.819105 English power-consumption cross-section LET-threshold SEU-robustness heavy-ion-tests memory-structure standard-CMOS-technology hardened-register SEU-testing PACS 85.42 Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Journal articles Journal articles Journal articles

A novel memory structure, designed to tolerate SEU perturbations, has been implemented in registers and tested. The design was completed using a standard submicron non-radiation hardened CMOS technology. This paper presents the results of heavy ion tests which evidence the noticeable improvement of the SEU-robustness with an increased LET threshold and reduced cross-section, without significant impact on the real estate, write time, or power consumption.

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