High Volume Processor Test Escape, an Analysis of Defect our Test are Missing, International Test Conference, pp.25-34, 1998. ,
Delay Test: The Next Frontier for LSSD Test Systems, Proceedings International Test Conference 1992, pp.578-596, 1992. ,
DOI : 10.1109/TEST.1992.527878
Quiescent power supply current measurement for CMOS IC defect detection, IEEE Transactions on Industrial Electronics, vol.36, issue.2, pp.2-211, 1989. ,
DOI : 10.1109/41.19071
Obtaining high defect coverage for frequency-dependent defects in complex ASICs, IEEE Design & Test of Computers, vol.20, issue.5, pp.46-52, 2003. ,
DOI : 10.1109/MDT.2003.1232256
Parametric Timing Failures and Defect Based Testing in Nanotechnology CMOS Digital ICs, Proc. of NASA Symp, 2003. ,
The Behavior and Testing Implications of CMOS IC Open Circuits, International Test Conf, pp.302-303, 1991. ,
On testing of interconnect open defects in combinational logic circuits with stems of large fanout, Proceedings. International Test Conference, pp.83-89, 2002. ,
DOI : 10.1109/TEST.2002.1041748
Topology dependence of floating gate faults in MOS integrated circuits, Electronics Letters, vol.22, issue.3, pp.152-153, 1986. ,
DOI : 10.1049/el:19860106
Resistance characterization for weak open defects Defect-Based Delay Testing of Resistive Vias Contacts: A Critical Evaluation Detectability Conditions for Interconnection Open Defects Testing for Resistive Opens and Stuck Opens Testing of Resistive Opens in CMOS Latches and Flip-Flops Defective Behaviors of Resistive Opens in Interconnect Lines Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighbouring die A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects On Hazard-Free Patterns for Fine Delay Fault Testing, Voltage and Current-based Fault Simulation for Interconnect Open Defects Trans. On Computer-Aided Design of IC and Systems International Test Conference International Test Conference International Test Conference International Conference on VLSI Design18] W. Qiu and D.M.H. Walker, " An Efficient Algorithm for Finding the K Longest Testable Paths Through each Gate in a Combinational Circuit International Test Conference International Test Conference, pp.1768-1779, 1999. ,