Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics

Abstract : Scan architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we discuss the issues of excessive peak power consumption during scan testing. We show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose a solution based on power-aware assignment of don't care bits in deterministic test patterns. For ISCAS'89 and ITC'99 benchmark circuits, this approach reduces peak power during the test cycle up to 89% compared to a random filling solution.
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Communication dans un congrès
IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. Design and Technology of Integrated Systems in Nanoscale Era, pp.359-364, 2006
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Soumis le : mercredi 13 septembre 2006 - 16:13:18
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : mardi 6 avril 2010 - 00:56:23

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Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, et al.. Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics. IEEE. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Sep 2006, Tunis, Tunisia. Design and Technology of Integrated Systems in Nanoscale Era, pp.359-364, 2006. 〈lirmm-00093690〉

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