M. Abramovici, P. R. Menon, and D. T. Miller, Critical Path Tracing ? An Alternative to Fault Simulation, IEEE Design & Test of Computers, vol.1, pp.1-83, 1984.
DOI : 10.1109/mdt.1984.5005582

S. Mitra and K. S. Kim, X-compact: an efficient response compaction technique for test cost reduction, Proceedings. International Test Conference, pp.311-320, 2002.
DOI : 10.1109/TEST.2002.1041774

G. Mrugalski, A. Pogiel, J. Rajski, J. Tyszer, and C. Wang, Fault diagnosis in designs with convolutional compactors, 2004 International Conferce on Test, pp.498-507, 2004.
DOI : 10.1109/TEST.2004.1386986

M. Abramovici and M. A. Breuer, Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis, IEEE Transactions on Computers, vol.29, issue.6, pp.451-460, 1980.
DOI : 10.1109/TC.1980.1675604

P. Girard, C. Landrault, and S. Pravossoudovitch, An advanced diagnostic method for delay faults in combinational faulty circuits, Journal of Electronic Testing, vol.5, issue.No 2, pp.3-277, 1995.
DOI : 10.1007/BF00996437

Y. Hsu and S. Gupta, A New Path- Oriented Effect-Cause Methodology to Diagnose Delay Failure, International Test Conference, pp.758-767, 1998.

S. Vendkataraman and W. , Kent Fuchs, « A Deductive Technique for Diagnosis of Bridging Fault, Internationel Conference on Computer Aided Design, pp.562-567, 1997.

X. Fan, W. Moore, C. Hora, and G. Gronthoud, A novel Stuck-At Based Method for Transistor Stuck-Open Fault Diagnosis, International Test Conference, session 16, pp.1-4, 2005.

D. B. Lavo, B. Chess, T. Larrabee, and F. Fergusson, Diagnosing realistic bridging faults with single stuck-at information, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, issue.3, pp.3-255, 1998.
DOI : 10.1109/43.700723

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.23.6479

P. Engelke, I. Polian, M. Renovell, and B. Becker, Simulating Resistive Bridging and Stuck-At Faults, International Test Conference, pp.1051-1059, 2003.
DOI : 10.1109/test.2003.1271093

URL : https://hal.archives-ouvertes.fr/lirmm-00269611

P. Girard, C. Landrault, and S. Pravossoudovitch, A novel approach to delay-fault diagnosis, [1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.357-360, 1992.
DOI : 10.1109/DAC.1992.227778

P. Girard, C. Landrault, and S. Pravossoudovitch, Delay-fault diagnosis based on critical path tracing from symbolic simulation, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems, pp.1133-1136, 1992.
DOI : 10.1109/ISCAS.1992.230327

. Rodriguez, Diagnostic of Path and Gate Delay Faults in Non-Scan Sequential Circuits, VTS'95: 13th IEEE VLSI Test Symposium, pp.380-386, 1995.

J. P. Hayes, Digital Simulation with Multiple Logic Values, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.5, issue.2, pp.274-283, 1986.
DOI : 10.1109/TCAD.1986.1270196