Asynchronous datapaths & the design of asynchronous adders " Formal Methods in systems design, 1992. ,
Preliminary discussion of the logical design of an electronic computing instrument structures; readings & examples, computer sciences series, Computer, 1971. ,
Self-timed adder with pipelined output, Proceedings of 36th Midwest Symposium on Circuits and Systems, 1993. ,
DOI : 10.1109/MWSCAS.1993.343203
A CMOS VLSI Implementation of an Asynchronous ALU, IFIP Working Conference on Asynchronous Design Methodologies, 1993. ,
The design of fast asynchronous adders and their implementation using DCVSL logic, IEEE International Symposium on Circuits and Systems, 1994. ,
Statistival Carry lookahead Adders, IEEE trans. on computers, vol.45, 1996. ,
Asynchronous sub-logarithmic adders, 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM. 10 Years Networking the Pacific Rim, 1987-1997, 1997. ,
DOI : 10.1109/PACRIM.1997.620314
Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits", IEEE Journal of Solid-State Circuits, vol.35, issue.10, 1998. ,
DOI : 10.1109/JSSC.2000.871333
Speculative completion for the design of high-performance asynchronous dynamic adders, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1997. ,
DOI : 10.1109/ASYNC.1997.587176
Arithmetic logic circuits using self-timed bit level dataflow & early evalutation, Proceedings of ICCD: VLSI in Computers & Processors, 2001. ,