R. D. Adams, High Performance Memory Testing, 2002.

R. D. Adams and E. S. Cooley, Analysis of Deceptive Destructive Read Memory Fault Model and Recommended Testing, IEEE North Atlantic Test Workshop, 1996.

R. D. Adams and E. S. Cooley, False write through and un-restored write electrical level fault models for SRAMs, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159), pp.27-32, 1997.
DOI : 10.1109/MTDT.1997.619391

Z. Al-ars and A. J. Van-de-goor, Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.496-503, 2001.
DOI : 10.1109/DATE.2001.915069

K. Baker, Defect-based delay testing of resistive vias-contacts a critical evaluation, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.467-476, 1999.
DOI : 10.1109/TEST.1999.805769

L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, and S. Borri, March iC-: An Improved Version of March C- for ADOFs Detection, 22nd IEEE VLSI Test Symposium, 2004. Proceedings., pp.129-134, 2004.
DOI : 10.1109/VTEST.2004.1299236
URL : https://hal.archives-ouvertes.fr/lirmm-00108772

L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri et al., March Tests Improvement for Address Decoder Open and Resistive Open Fault Detection, Proc. Latin American Workshop, pp.31-36, 2004.

L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri et al., Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 2004.
DOI : 10.1109/ETSYM.2004.1347645

A. J. Van-de-goor, Using march tests to test SRAMs, IEEE Design & Test of Computers, vol.10, issue.1, pp.8-14, 1993.
DOI : 10.1109/54.199799

A. J. Van-de-goor, Testing Semiconductor Memories, Theory and Practice, Gouda, The Netherlands, 1998.

A. J. Van-de-goor and Z. , Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-289, 2000.
DOI : 10.1109/VTEST.2000.843856

A. J. Van-de-goor and J. De-neef, Industrial Evaluation of DRAM Tests, Proc. Design Automation and Test in Europe, pp.623-630, 1999.

S. Hamdioui, Z. Al-ars, and A. J. Van-de-goor, Testing static and dynamic faults in random access memories, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), pp.395-400, 2002.
DOI : 10.1109/VTS.2002.1011170

C. James, Testing for Resistive Opens and Stuck Opens, Proc. Int'l Test Conf, pp.1049-1058, 2001.

M. Marinescu, Simple and Efficient Algorithms for Functional RAM Testing, Proc. Int'l Test Conf, pp.236-239, 1982.

W. Needham, High volume microprocessor test escapes, an analysis of defects our tests are missing, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.25-34, 1998.
DOI : 10.1109/TEST.1998.743133

D. Niggemeyer, M. Redeker, and J. Otterstedt, Integration of Non-classical Faults in Standard March Tests Records of the IEEE Int, Memory Technology, Design and Testing, pp.91-96, 1998.

J. Otterstedt, Detection of CMOS address decoder open faults with March and pseudo random memory tests, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.53-62, 1998.
DOI : 10.1109/TEST.1998.743137

R. Rodriquez, Resistance Characterization of Interconnect Weak and Strong Open Defects, IEEE Design & Test of Computers, vol.19, issue.5, pp.18-26, 2002.

M. Sachdev, Test and testability techniques for open defects in RAM address decoders, Proceedings ED&TC European Design and Test Conference, pp.428-434, 1996.
DOI : 10.1109/EDTC.1996.494336

M. Sachdev, Open defects in CMOS RAM address decoders, IEEE Design & Test of Computers, vol.14, issue.2, pp.26-33, 1997.
DOI : 10.1109/54.587738

I. Schanstra and A. J. Van-de-goor, Industrial evaluation of stress combinations for march tests applied to SRAMs, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.983-992, 1999.
DOI : 10.1109/TEST.1999.805831

K. Zarrineh, Defect analysis and realistic fault model extensions for static random access memories, Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp.119-124, 2000.
DOI : 10.1109/MTDT.2000.868625