Temperature Dependency in UDSM Process

Abstract : In low power UDSM process the use of reduced supply voltage with high threshold voltages may reverse the temperature dependence of designs. In this paper we propose a model to define the true worst Process, Voltage and Temperature conditions to be used to verify a design. This model will provide an accurate worst case definition for high performance designs where standard design margins are not applicable. This model is validated at either cell level or path level on two different 130nm process.
Type de document :
Communication dans un congrès
PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (3728), pp.693-703, 2005, 〈10.1007/11556930_71〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106077
Contributeur : Christine Carvalho de Matos <>
Soumis le : vendredi 13 octobre 2006 - 10:23:07
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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Benoit Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Temperature Dependency in UDSM Process. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation, LNCS (3728), pp.693-703, 2005, 〈10.1007/11556930_71〉. 〈lirmm-00106077〉

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