S. Akers, Binary Decision Diagrams, IEEE Transactions on Computers, vol.27, issue.6, pp.509-516, 1978.
DOI : 10.1109/TC.1978.1675141

A. Kuelmann and F. ?krohm, Equivalence Checking Using Cuts and Heaps, Design Automation Conference (DAC) 1997, pp.263-268

S. M. Reddy, W. ?kunz, and D. K. ?pradhan, Novel verification framework combining structural and OBDD methods in a synthesis environment, Proceedings of the 32nd ACM/IEEE conference on Design automation conference , DAC '95, pp.414-419
DOI : 10.1145/217474.328705

D. Brand, Verification of Large Synthesized Designs, IEEE International Conference on Computer-Aided Design (ICCAD), pp.534-537, 1993.

C. Van-eijk, Formal Methods for the Verification of Digital Circuits, 1997.

J. R. Burch, Symbolic model checking for sequential circuit verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.13, issue.4, pp.401-424, 1994.
DOI : 10.1109/43.275352

S. Rahim, B. ?rouzeyre, L. ?torres, and J. ?rampon, Loop Problem in Sequential Equivalence Checking, pp.52-58, 2002.

J. R. Burch and V. ?singhal, Robust latch mapping for combinational equivalence checking, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, pp.563-569, 1998.
DOI : 10.1145/288548.289087

C. Van-eijk, Sequential equivalence checking without state space traversal, Proceedings Design, Automation and Test in Europe, pp.618-623, 1998.
DOI : 10.1109/DATE.1998.655922

S. Rahim, B. ?rouzeyre, L. ?torres, and J. ?rampon, An Efficient Flip-Flops Matching Engine, DDECS (IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems), Stará Lesná, 2004.
URL : https://hal.archives-ouvertes.fr/lirmm-00108773

S. Rahim, B. ?rouzeyre, L. ?torres, and J. ?rampon, An Equivalence Checking Flow to Verify Sequential Optmizations In poster session of Formal Methods and Models for Codesign, 2004.

S. Rahim, Equivalence Checking for Sequentially Optimized Designs, 2004.

S. Rahim, B. ?rouzeyre, L. ?torres, and J. ?rampon, Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking, Eighth IEEE International High-Level Design Validation and Test Workshop, pp.129-135, 2003.
DOI : 10.1109/HLDVT.2003.1252486
URL : https://hal.archives-ouvertes.fr/lirmm-00269474

S. Huang, K. ?cheng, K. ?chen, and U. ?glaeser, An ATPG-Based Framework for Verifying Sequential Equivalence, In ITC, pp.865-874, 1996.

S. Huang and K. ?cheng, AQUILA: A Local BDD-based Equivalence Verifier, Informal Equivalence Checking and Design Debugging, pp.90-109
DOI : 10.1007/978-1-4615-5693-0_5

Ê. Bruno and M. S. Received, PhD degree in CAD in 1984 and HabilitationáHabilitation´Habilitationá diriger les recherches " in 1992, all degrees from the University of Montpellier , France. Currently he is Professor at the University of Montpellier where he heads the electronic engineering school. He does his research at LIRMM. His main research interests include synthesis and test of integrated circuits and formal verification, 1978.