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A Compact DC Model of Gate Oxide Short Defect

Rachid Bouchakour 1 Jean-Michel Portal 1 Jean-Marc Galliere 2 Florence Azaïs 3 Yves Bertrand 3 Michel Renovell 3
1 L2MP - Laboratoire matériaux et microélectronique de Provence
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper a new electrical transistor compact model including a gate oxide short defects is proposed based on a charge sheet model approach. The basic equations and the topology of the model are presented in detail. It is demonstrated that the electrical behaviour of the proposed model matches in a satisfactory way the defective transistor behaviour.
Keywords : MOS defect modelling Gate oxide short
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Journal articles
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108564
Contributor : Christine Carvalho de Matos <>
Submitted on : Monday, October 23, 2006 - 7:43:12 AM
Last modification on : Tuesday, September 24, 2019 - 12:04:01 PM

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | UNIV-TLN | UNIV-AMU

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Rachid Bouchakour, Jean-Michel Portal, Jean-Marc Galliere, Florence Azaïs, Yves Bertrand, et al.. A Compact DC Model of Gate Oxide Short Defect. Microelectronic Engineering, Elsevier, 2004, 72 (1-4), pp.140-148. ⟨10.1016/j.mee.2003.12.051⟩. ⟨lirmm-00108564⟩

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