Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-289, 2000. ,
DOI : 10.1109/VTEST.2000.843856
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.496-503, 2001. ,
DOI : 10.1109/DATE.2001.915069
Test and testability techniques for open defects in RAM address decoders, Proceedings ED&TC European Design and Test Conference, pp.428-434, 1996. ,
DOI : 10.1109/EDTC.1996.494336
Open defects in CMOS RAM address decoders, IEEE Design & Test of Computers, vol.14, issue.2, pp.26-33, 1997. ,
DOI : 10.1109/54.587738
Comparison of open and Resistive-Open Defect Test Conditions in SRAM Address Decoders, Proc. Asian Test Symposium, pp.250-255, 2003. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01238821
Detection of CMOS address decoder open faults with March and pseudo random memory tests, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.53-62, 1998. ,
DOI : 10.1109/TEST.1998.743137
A Microcode-based Memory BIST Implementing Modified March Algorithm, Proc. Asian Test Symposium, pp.391-395, 2001. ,
Detection of Delay Faults in Memory Address Decoder, Journal of Electronic Testing, vol.16, issue.4, pp.381-387, 2000. ,
DOI : 10.1023/A:1008322103755
Tests for resistive and capacitive defects in address decoders, Proceedings 10th Asian Test Symposium, pp.31-36, 2001. ,
DOI : 10.1109/ATS.2001.990255
Integration of non-classical faults in standard March tests, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236), 1998. ,
DOI : 10.1109/MTDT.1998.705953
March Tests Improvement for Address Decoder Open and Resistive Open Faults Detection, 2004. ,
An Efficient Built-In Self-Test Scheme for Functional Test of Embedded Memories, Proc. Int. Symposium Fault Tolerant Computing, 1985. ,
Simple and Efficient Algorithms for Functional RAM Testing, Proc. Int. Test Conf, pp.236-239, 1982. ,
Defect-oriented dynamic fault models for embedded-SRAMs, The Eighth IEEE European Test Workshop, 2003. Proceedings., pp.23-28, 2003. ,
DOI : 10.1109/ETW.2003.1231664
URL : https://hal.archives-ouvertes.fr/lirmm-00269526
Theory of transparent BIST for RAMs, IEEE Transactions on Computers, vol.45, issue.10, pp.1141-1155, 1996. ,
DOI : 10.1109/12.543708
URL : https://hal.archives-ouvertes.fr/hal-00013890