Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-289, 2000. ,
DOI : 10.1109/VTEST.2000.843856
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.496-503, 2001. ,
DOI : 10.1109/DATE.2001.915069
Importance of dynamic faults for new SRAM technologies, The Eighth IEEE European Test Workshop, 2003. Proceedings., pp.29-34, 2003. ,
DOI : 10.1109/ETW.2003.1231665
Testing static and dynamic faults in random access memories, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), pp.395-400, 2002. ,
DOI : 10.1109/VTS.2002.1011170
Defect-oriented dynamic fault models for embedded-SRAMs, The Eighth IEEE European Test Workshop, 2003. Proceedings., pp.23-28, 2003. ,
DOI : 10.1109/ETW.2003.1231664
URL : https://hal.archives-ouvertes.fr/lirmm-00269526
Simple and Efficient Algorithms for Functional RAM Testing, Proc. Int. Test Conf, pp.236-239, 1982. ,
Testing Semiconductor Memories: Theory and Practice, 1998. ,
Integration of non-classical faults in standard March tests, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236), pp.91-96, 1998. ,
DOI : 10.1109/MTDT.1998.705953
Resistance Characterization of Interconnect Weak and Strong Open Defects, IEEE Design & Test of Computers, vol.195, pp.18-26, 2002. ,
Analysis of a Deceptive Destructive Read Memory Fault Model and Recommended Testing, Proc. IEEE North Atlantic Test Workshop, 1996. ,