A. J. Van-de-goor, Using march tests to test SRAMs, IEEE Design & Test of Computers, vol.10, issue.1, pp.8-14, 1993.
DOI : 10.1109/54.199799

M. Sachdev, Test and testability techniques for open defects in RAM address decoders, Proceedings ED&TC European Design and Test Conference, pp.428-434, 1996.
DOI : 10.1109/EDTC.1996.494336

R. D. Adams and E. S. Cooley, Analysis of Deceptive Destructive Read Memory Fault Model and Recommended Testing, IEEE North Atlantic Test Workshop, 1996.

R. D. Adams and E. S. Cooley, False write through and un-restored write electrical level fault models for SRAMs, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159), pp.27-32, 1997.
DOI : 10.1109/MTDT.1997.619391

K. Zarrineh, Defect analysis and realistic fault model extensions for static random access memories, Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp.119-124, 2000.
DOI : 10.1109/MTDT.2000.868625

A. J. Van-de-goor, Testing Semiconductor Memories, Theory and Practice, 1998.

R. D. Adams, High Performance Memory Testing, 2002.

K. Baker, Defect-based delay testing of resistive vias-contacts a critical evaluation, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.467-476, 1999.
DOI : 10.1109/TEST.1999.805769

C. James, Testing for Resistive Opens and Stuck Opens, Proc. Int. Test Conference, pp.1049-1058, 2001.

W. Needham, High volume microprocessor test escapes, an analysis of defects our tests are missing, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.25-34, 1998.
DOI : 10.1109/TEST.1998.743133

A. J. Van-de-goor and Z. , Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-289, 2000.
DOI : 10.1109/VTEST.2000.843856

S. Hamdioui, A. J. Ars, and . Van-de-goor, Testing static and dynamic faults in random access memories, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), pp.395-400, 2002.
DOI : 10.1109/VTS.2002.1011170

L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri et al., Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 2004.
DOI : 10.1109/ETSYM.2004.1347645

M. Marinescu, Simple and Efficient Algorithms for Functional RAM Testing, Proc. Int. Test Conf, pp.236-239, 1982.

A. J. Van-de-goor, Testing Semiconductor Memories: Theory and Practice, 1998.

D. Niggemeyer, M. Redeker, and J. Otterstedt, Integration of non-classical faults in standard March tests, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236), pp.91-96, 1998.
DOI : 10.1109/MTDT.1998.705953

S. Borri, M. Hage-hassan, P. Girard, S. Pravossoudovitch, and A. Virazel, Defect-oriented dynamic fault models for embedded-SRAMs, The Eighth IEEE European Test Workshop, 2003. Proceedings., pp.23-28, 2003.
DOI : 10.1109/ETW.2003.1231664
URL : https://hal.archives-ouvertes.fr/lirmm-00269526

A. S. Sedra and K. C. Smith, Microelectronic circuit, pp.120-122, 1998.

R. Rodriquez, Resistance Characterization of Interconnect Weak and Strong Open Defects, IEEE Design & Test of Computers, vol.195, pp.18-26, 2002.