M. Abramovici, C. Stroud, C. Hamilton, S. Wijesuriya, and V. Verma, Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.973-982, 1999.
DOI : 10.1109/TEST.1999.805830

M. Abramovici and C. Stroud, BIST-based delay-fault testing in FPGAs, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), pp.131-134, 2002.
DOI : 10.1109/OLT.2002.1030195

V. Betz, J. Rose, and A. Marquardt, Architecture Deep- Submicron FPGAs, 1999.
DOI : 10.1007/978-1-4615-5145-4

R. A. Carberry, S. P. Young, and T. J. Bauer, FPGA LookUp Table with High Speed Read Decoder, 2003.

E. Chmelar, FPGA Interconnect Delay Fault Testing, IEEE Proc. of Int. Test Conf, pp.1239-1247, 2003.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Páez-monzón et al., The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, issue.3, pp.321-330, 1999.
DOI : 10.1109/92.784093

P. Girard, O. Héron, S. Pravossoudovitch, and M. , Defect analysis for delay-fault BIST in FPGAs, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., pp.124-128, 2003.
DOI : 10.1109/OLT.2003.1214378
URL : https://hal.archives-ouvertes.fr/lirmm-00269553

P. Girard, O. Héron, S. Pravossoudovitch, and M. , Requirements for delay testing of look-up tables in SRAM-based FPGAs, The Eighth IEEE European Test Workshop, 2003. Proceedings., pp.147-152, 2003.
DOI : 10.1109/ETW.2003.1231682
URL : https://hal.archives-ouvertes.fr/lirmm-00269530

P. Girard, O. Héron, S. Pravossoudovitch, and M. , High Quality TPG for Delay Faults in Look-Up Tables of FPGAs, Second IEEE International Workshop on Electronic Design, Test and Applications, pp.83-88, 2000.
DOI : 10.1109/DELTA.2004.10052
URL : https://hal.archives-ouvertes.fr/lirmm-00108830

I. G. Harris, P. R. Menon, and R. Tessier, BIST-based delay path testing in FPGA architectures, Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.364-369, 2001.
DOI : 10.1109/TEST.2001.966717

W. K. Huang, F. J. Meyer, X. T. Chen, and F. Lombardi, Testing configurable LUT-based FPGA's, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.6, issue.2, pp.276-283, 1998.
DOI : 10.1109/92.678888

A. Krasniewski, Application-dependent testing of FPGA delay faults, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium, pp.260-267, 1999.
DOI : 10.1109/EURMIC.1999.794478

A. Krasniewski, Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs, IEEE Proc. of Int. Conf. on Field Programmable Logic & Applications, pp.675-684, 2000.
DOI : 10.1007/3-540-44614-1_72

M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, SRAM-Based FPGAs: Testing the Embedded RAM Modules, JETTA, vol.14, pp.159-167, 1999.

M. Renovell, J. M. Portal, P. Faure, J. Figueras, and Y. Zorian, Analyzing the test generation problem for an application-oriented test of FPGAs, Proceedings IEEE European Test Workshop, pp.157-162, 2000.
DOI : 10.1109/ETW.2000.873782

M. Renovell and Y. Zorian, Different experiments in test generation for XILINX FPGAs, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.854-861, 2000.
DOI : 10.1109/TEST.2000.894292

C. Stroud, S. Konola, P. Chen, and M. Abramovici, Built- In Self Test of Logic Blocks in FPGAs, IEEE Proc. of VLSI Test Symp, pp.387-392, 1996.

C. Stroud, E. Lee, and M. Abramovici, Built-in self-test of FPGA interconnect, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.404-411, 1998.
DOI : 10.1109/TEST.1998.743180

M. B. Tahoori, Testing for resistive open defects in FPGAs, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings., pp.332-335, 2002.
DOI : 10.1109/FPT.2002.1188704

X. Inc, Virtex Series Product Specification (FPGAs), pp.2-6, 2002.