Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint, IEEE Int. Test Conf, pp.488-493, 2003. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00269609
Essentials of Electronic Testing, 2000. ,
Survey of Low-Power Testing of VLSI Circuits, IEEE Design & Test of Computers, vol.19, pp.82-92, 2002. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00268584
, IEEE European Test Workshop, pp.49-53, 1998.
ATPG for Heat Dissipation Minimization for Scan Testing, pp.614-619, 1997. ,
A Test Pattern Generation Methodology for Low Power Consumption, IEEE VLSI Test Symp, pp.453-459, 1998. ,
A Scheme to Reduce Power Consumption During Scan Testing, IEEE Int. Test Conf, pp.670-677, 2001. ,
Static Compaction Techniques to Control Scan Vector Power Dissipation, IEEE VLSI Test Symp, pp.35-42, 2000. ,
Reducing Power Dissipation During Test Using Scan Chain Disable, IEEE VLSI Test Symp, pp.319-324, 2001. ,
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores, IEEE Asian Test Symp, pp.253-258, 2001. ,
Peak-Power Reduction for Multiple-Scan Circuits during Test Application, IEEE Asian Test Symp, pp.453-458, 2000. ,
Combining Low-Power Scan Testing and Test Data Compression for System, ACM/IEEE Design Auto. Conf, pp.166-169, 2001. ,
Power Constraint Scheduling of Tests, IEEE Int. Conf. on VLSI Design, pp.271-274, 1994. ,
Precedence-Based, Preemptive, and Power-constrained Test Scheduling for Systemon-a-Chip, IEEE VLSI Test Symp, pp.368-374, 2001. ,
Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuits, IEEE Transactions on CAD, vol.17, pp.1325-1333, 1998. ,
Power Driven Chaining of Flip-flops in Scan Architectures, IEEE Int. Test Conf, pp.796-803, 2002. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00268492
A New Approach to Scan Chain Reordering Using Physical Design Information, IEEE Int. Test Conf, pp.348-355, 1998. ,
A Layout-Based Approach for Ordering Scan Chain Flip-flops, IEEE Int. Test Conf, pp.341-347, 1998. ,
Integrating DFT in the Physical Synthesis Flow, IEEE Int. Test Conf, pp.788-795, 2002. ,
An Efficient Linear-Time Algorithm for Scan Chain Optimization and Repartitioning, IEEE Int. Test Conf, pp.781-787, 2000. ,
Combinational Profiles of Sequential Benchmark Circuits, IEEE Int. Symp. on Circuits and Systems, pp.1929-1934, 1989. ,
, , 2000.
, , 1999.