Test data compression for system-on-chip using golomb codes, VTS'00, pp.113-120 ,
A geometricprimitives-based compression scheme for testing system-onchip, pp.54-59 ,
Scan vector compression/decompression using statistical coding, VTS'99, pp.114-120 ,
Reducing test data volume using external/LBIST hybrid test patterns, pp.115-122 ,
A mixed mode BIST scheme based on reseeding of folding counters, pp.778-784 ,
Test volume application time reduction through scan chain concealment, vol.01, pp.151-155 ,
On reducing test data volume and test application time for multiple scan chain designs, pp.341-346 ,
virtual scan chain: A means for reducing scan length in cores, VTS'00, pp.73-78 ,
Accumulator based deterministic BIST, ITC, vol.98, pp.412-421 ,
Embeded Deterministic Test for Low cost Manufacturing Test, Proc. ITC, pp.301-310, 2002. ,
OPMISR: The foundation for compressed ATPG vectors, pp.748-757 ,
Twodimensional test data compression for scan-based deterministic BIST, pp.291-298 ,
Configuring Arithmetic pattern generators and response compactors from the RT-module of a Circuit, Proc. ATS 98, pp.15-20 ,
On using Test Vector Differences for Reducing Test Pin Numbers, Proc. DELTA, 2004. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00108832