Delay Bound Based CMOS Gate Sizing Technique
Abstract
In this paper we address the problem of delay constraint distribution on CMOS combinatorial paths. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on Newton-Raphson like algorithms. Validation is obtained on a 0.25µm process by comparing the different constraint distribution techniques on various benchmarks.
Fichier principal
Delay_bound_based_CMOS_gate_sizing_technique.pdf (365.8 Ko)
Télécharger le fichier
| Origin | Publisher files allowed on an open archive |
|---|
Loading...