J. M. Shyu-&al and A. Dunlop, Optimization-based transistor sizing, IEEE J. Solid State Circuits, vol.23, pp.400-409, 1988.

J. Fishburn and A. Dunlop, TILOS: a posynomial programming approach to transistor sizing, Proc. Design Automation Conf, pp.326-328, 1985.

C. Mead and M. Rem, Minimum propagation delays in VLSI, IEEE J. Solid State Circuits, vol.17, pp.773-775, 1982.

I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, 1999.

K. O. Jeppson, Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay, IEEE J. Solid State Circuits, vol.29, pp.646-654, 1994.

S. Chakraborty and R. Murgai, Layout driven timing optimization by generalized DeMorgan transform, IWLS, pp.53-59, 2001.

M. Ketkar, K. Kasamsetty, and S. Sapatnekar, Convex delay models for transistor sizing, Proc. of the 2000 Design Automation Conf, pp.655-660

J. , A delay model for logic synthesis of continuously-sized networks, ICCAD 95, 1995.

R. K. Brayton and R. Spence, Sensitivity and Optimization, 1980.