J. M. Shyu, A. Sangiovanni-vincentelli, J. Fishburn, and A. Dunlop, Optimization-based transistor sizing, IEEE J. Solid State Circuits, vol.23, pp.400-409, 1988.

J. P. Fishburn and A. E. Dunlop, Tilos : a posynomial programming approach to transistor sizing, Proc. IEEE Int. Conf. Computer-Aided Design, pp.326-328, 1985.

S. S. Sapatnekar, V. B. Rao, P. M. Vaidya, and S. M. Kang, An exact solution to the transistor sizing problem for CMOS circuits using convex functions, pp.1621-1634, 1993.

I. E. Sutherland, B. Sproull, and D. Harris, Logical effort, designing fast cmos circuits, 1999.

S. R. Vemuru, A. R. Thorbjornsen, and A. A. Tuszynski, CMOS tapered buffer, IEEE J. Solid State Circuits, vol.26, pp.1265-1269, 1991.

Y. Jiang, S. S. Sapatnekar, C. Bamji, and J. Kim, Interleaving buffer insertion and transistor sizing into a single optimization, IEEE Trans. on VLSI, pp.625-633, 1998.

P. G. Paulin and F. J. Poirot, Logic decomposition algorithm for the timing optimization of multilevel logic, Proc. ICCD 89, pp.329-333

D. Singh, J. M. Rabaey, M. Pedram, F. Catthoor, S. Rajgopal et al., Power Conscious CAD tools and Methodologies: a Perspective, Proc. IEEE, vol.83, pp.570-593, 1995.

H. C. Chen, D. H. Du, and L. R. Liu, Critical Path Selection for Performance Optimization, IEEE trans. On CAD of Integrated Circuits and Systems, vol.12, pp.185-195, 1995.

N. Azemard and D. Auvergne, POPS : A tool for delay/power performance optimization, Journal of Systems Architecture, vol.47, pp.375-382, 2001.
URL : https://hal.archives-ouvertes.fr/lirmm-00239314

S. Yen, D. Du, and S. Ghanta, Efficient Algorithms for Extracting the k Most Critical Paths in Timing Analysis, Design Automation Conference, pp.649-654, 1989.

S. Cremoux, N. Azemard, and D. Auvergne, Path resizing based on incremental technique, Proc. ISCAS, 1998.
URL : https://hal.archives-ouvertes.fr/lirmm-00241190

K. O. Jeppson, Modeling the Influence of the Transistor Gain Ratio and the Input-toOutput Coupling Capacitance on the CMOS Inverter Delay, IEEE JSSC, vol.29, pp.646-654, 1994.

P. Maurine, M. Rezzoug, N. Azémard, and D. Auvergne, Transition time modeling in deep submicron CMOS, IEEE trans. on Computer Aided Design, vol.21, pp.1352-1363, 2002.
URL : https://hal.archives-ouvertes.fr/lirmm-00239324

M. Mead and . Rem, Minimum propagation delays in VLSI, IEEE J. Solid State Circuits, vol.17, pp.773-775, 1982.