In low power UDSM process the combined use of reduced value of the supply voltage and high threshold voltage value may greatly modify the temperature sensitivity of designs, which becomes structure and transition edge dependent. In this paper we propose a model for determining the temperature coefficient of CMOS structures and defining the worst Process, Voltage and Temperature condition to be verified for qualifying a design. This model is validated on two 0.13μm processes by comparing the calculated values of the temperature coefficient of the performance parameters to values deduced from electrical simulations (Eldo). Application to combinatorial path gives evidence of the occurrence of temperature inversion that is structure and control condition dependent and must carefully be considered for robust design validation.