C. Park, Reversal of temperature dependence of integrated circuits operating at very low voltages, Proc. IEDM conference, pp.71-74, 1995.

S. M. Sze, Physics of semiconductor devices, 1983.

S. Inc, Scalable Polynomial Delay And Power Model, 2002.

B. Lasbouygues, J. Schindler, S. Engels, P. Maurine, N. Azemard et al., Continuous representation of the performance of a CMOS library, ESSIRC'03 Conf. on 16-18, 2003.
URL : https://hal.archives-ouvertes.fr/lirmm-00239459

P. Maurine, M. Rezzoug, N. Azemard, and D. Auvergne, Transition time modeling in deep submicron CMOS, IEEE Trans. on Computer Aided Design, vol.21, pp.1352-1363, 2002.
URL : https://hal.archives-ouvertes.fr/lirmm-00239324

T. Sakurai and A. R. Newton, Alpha-power model, and its application to CMOS inverter delay and other formulas, J. Solid State Circuits, vol.25, pp.584-594, 1990.

K. O. Jeppson, Modeling the Influence of the Transistor Gain Ratio and the Input-toOutput Coupling Capacitance on the CMOS Inverter Delay, IEEE JSSC, vol.29, pp.646-654, 1994.

J. M. Daga, E. Ottaviano, and D. Auvergne, Temperature effect on delay for low voltage applications, Design, Automation and Test in Europe, Proc, pp.23-26, 1998.

J. A. Power, An Investigation of MOSFET Statistical and Temperature Effects, Proc. IEEE 1992 Int. Conference on Microelectronic Test Structures, vol.5, 1992.

A. Osman, An Extended Tanh Law MOSFET Model for High Temperature Circuit Simulation, IEEE JSSC, vol.30, 1995.