W. J. Dally and A. Chang, The role of custom design in ASIC chips, proc. 37 th design automation Conference, pp.643-647, 2000.

R. Reis, D. Reis, M. Auvergne, and . Robert, The Library Free Technology Mapping Problem, IWLS, vol.2, pp.7-8, 1997.

L. Landrault, A. Pellier, C. Richard, M. Jay, D. Robert et al., DCIS'03, XVIII Design of Circuits and Integrated Systems Conference, pp.266-271, 2003.

N. Azemard and D. Auvergne, POPS : A tool for delay/power performance optimization, Journal of Systems Architecture, vol.47, pp.375-382, 2001.
URL : https://hal.archives-ouvertes.fr/lirmm-00239434

D. Mcmillen, M. Butts, R. Composano, D. Hill, and T. W. Williams, An Industrial View of Electronic Design Automation, IEEE Transactions on Computer, vol.19, pp.1428-1448, 2000.

K. Keutzer and . Scott, Improving Cell Library for synthesis, Proc. Of the International Workshop on Logic Synthesis, 1993.

K. Keutzer, K. Kolwicz, and M. Lega, Impact of Library Size on the Quality of Automated Synthesis, pp.120-123, 1987.

P. De-dood, Approach makes most of synthesis, place and route -Liquid Cell ease the flow, EETimes, p.1183, 2001.

A. D. Lopez and H. S. Law, A Dense Gate-Matrix Layout for MOS VLSI, IEEE Transactions on Electron Devices, issue.8, pp.1671-1675, 1980.

F. Moraes, R. Reis, L. Torres, M. Robert, and D. Auvergne, Pre-Layout Performance Prediction For Automatic Macro-Cell Synthesis, vol.96, pp.814-817, 1996.

M. Fiduccia and R. M. Mattheyses, A linear-time heuristics for improving network partitions, Proceedings of the 19th Design Automation Conference, pp.175-181, 1982.

M. A. Riepe and K. A. Sakallah, Transistor level micro-placement and routing for two dimensional digital VLSI cell synthesis, p.99

C. A. Monterey and . Usa,

M. Maxfield, Delay effects Rule in Deep-Submicron Ics, pp.109-121, 1995.

S. W. Cheng, H. C. Chen, D. H. Du, and A. Lim, the Role of Long and Short Paths in Circuit Performance Optimization, IEEE trans. On CAD of I.C. and Systems, vol.13, pp.857-864, 1994.

R. Murgai, On the Global Fanout Optimization Problem, 1999.

C. L. Berman, J. L. Carter, and K. F. Day, The Fanout Problem: From Theory to Practice, Advanced Research in VLSI: Proceedings of the 1989 Decennial Caltech Conferences, pp.69-99, 1989.

H. C. Chen, D. H. Du, and L. R. Liu, Critical Path Selection for Performance Optimization, IEEE trans. On CAD of Integrated Circuits and Systems, vol.12, pp.185-195, 1995.