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Conference Papers Year : 2004

RC on-chip interconnect Performance revisited

Abstract

The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in sub-micrometer domain due to the inability of a so simple model in capturing input slope effects. This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of inverter transition time and switching delay, we propose a model of the shielding capacitance effect on the input driver. We determine the transition time of the output driver and the switching delay of the complete structure for various sets of line parameters and different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on a 0.13µm process, using the ELDO's transmission line model.
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Dates and versions

lirmm-00108934 , version 1 (21-01-2017)

Identifiers

  • HAL Id : lirmm-00108934 , version 1

Cite

Philippe Maurine, Nadine Azemard, Daniel Auvergne. RC on-chip interconnect Performance revisited. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. pp.809-814. ⟨lirmm-00108934⟩
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