Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Book Sections Year : 2006

Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs

Régis Roubadia
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Sami Ajram
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Abstract

This paper introduces two low power design techniques to improve both the jitter and phase noise of PLL frequency synthesizers used in ASICs. These techniques focus on the noise current reduction in wideband ring VCOs. Two PLLs embedding such VCOs were implemented, in 0.18μm and 0.13μm CMOS technologies, under 1.8V and 1.2V supply voltages respectively. The maximum improvement was observed for a 1.8V PLL running at 160MHz and consuming 1.6mW, which phase noise was reduced from -81.4dBc/Hz to -88.4dBc/Hz.

Dates and versions

lirmm-00109058 , version 1 (23-10-2006)

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Régis Roubadia, Sami Ajram, Guy Cathébras. Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs. Nadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.458-467, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩. ⟨lirmm-00109058⟩
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