A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Reports (Research Report) Year : 2004

A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect

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Micro and nanotechnologies/Microelectronics

Christine Carvalho De Matos  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00109221

Submitted on : Tuesday, October 24, 2006-7:42:09 AM

Last modification on : Tuesday, December 5, 2023-6:08:07 PM

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lirmm-00109221 , version 1 (24-10-2006)

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  • HAL Id : lirmm-00109221 , version 1

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Michel Renovell, Jean-Marc J.-M. Galliere, Florence Azaïs, Yves Bertrand, Jean-Michel Portal. A Compact Model for Electrical Simulation of MOS Transistor with Gate Oxide Short Defect. [Research Report] 04080, Lirmm, University of Montpellier. 2004. ⟨lirmm-00109221⟩

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