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Security Evaluation of Dual Rail Logic Against DPA Attacks Hanitriniaina Razafindraibe 175150-0 Philippe Maurine 95c9402fd23112808a8f6dfbc6fe5eaf lirmm.fr philippe-maurine 22073 40706-22073 https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate https://www.idref.fr/144880717 https://orcid.org/0000-0002-9706-5710 https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr Michel Robert 9c0d7463dc45ca4a00f86b4653d59e36 lirmm.fr michel-robert 938334 107144-938334 https://orcid.org/0000-0002-5075-2898 Marc Renaudin 204579-0 Martine Peridier c2991973e5c01c2376ee6dbe9de59840 lirmm.fr.invalid 2006-10-25 12:36:36 2026-03-26 11:44:10 2006-10-26 09:14:05 2006-10-16 2006-10-25 contributor Martine Peridier c2991973e5c01c2376ee6dbe9de59840 lirmm.fr.invalid CCSD lirmm-00109692 https://hal-lirmm.ccsd.cnrs.fr/lirmm-00109692 razafindraibe:lirmm-00109692 <i>VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration</i>, Oct 2006, Nice, France. pp.181-186, <a target="_blank" href="https://dx.doi.org/10.1109/VLSISOC.2006.313230">⟨10.1109/VLSISOC.2006.313230⟩</a> VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration, Oct 2006, Nice, France. pp.181-186, ⟨10.1109/VLSISOC.2006.313230⟩ HAL Authorization HAL Grenoble Alpes CNRS - Centre national de la recherche scientifique Université Joseph Fourier - Grenoble I Institut polytechnique de Grenoble Techniques of Informatics and Microelectronics for integrated systems Architecture SysMic Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier MIC Département Microélectronique Mathématiques, Informatique, Physique et Systèmes Université de Montpellier Université de Montpellier (2015-2021) TEST-UGA International No No Yes Yes Security Evaluation of Dual Rail Logic Against DPA Attacks Hanitriniaina Razafindraibe 175150-0 Philippe Maurine 95c9402fd23112808a8f6dfbc6fe5eaf lirmm.fr philippe-maurine 22073 40706-22073 https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate https://www.idref.fr/144880717 https://orcid.org/0000-0002-9706-5710 https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr Michel Robert 9c0d7463dc45ca4a00f86b4653d59e36 lirmm.fr michel-robert 938334 107144-938334 https://orcid.org/0000-0002-5075-2898 Marc Renaudin 204579-0 3-901882-19-7 VLSI-SoC 2006 - 14th IFIP International Conference on Very Large Scale Integration 2006-10-16 2006-10-18 Nice France IEEE 181-186 2006 10.1109/VLSISOC.2006.313230 English Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Conference papers Conference papers Conference papers

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA attacks of dual rail logic is carried out. The result of this investigation, performed on 130nm process, is the formal identification of the design range in which dual rail logic can be considered as robust.

139590827 0000000405990488 199111950H https://ror.org/013yean28 Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier LIRMM 1995-01-01 2021-12-31

161 rue Ada - 34095 Montpellier

https://www.lirmm.fr Conception et Test de Systèmes MICroélectroniques SysMIC

http://www.lirmm.fr/recherche/equipes/sysmic 02901364X 0000 0001 2337 0176 200311834E https://ror.org/000063q30 Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés TIMA 1995-01-01 2015-12-31

46 avenue Félix Viallet38031 GRENOBLE Cedex 1

http://tima.univ-grenoble-alpes.fr/ 0000000120970141 https://ror.org/051escj72 Université de Montpellier UM 2021-12-31

163 rue Auguste Broussonnet - 34090 Montpellier

http://www.umontpellier.fr/ 02636817X 0000000122597504 https://ror.org/02feahw73 Centre National de la Recherche Scientifique CNRS 1939-10-19

https://www.cnrs.fr/ 026404796 https://ror.org/02aj0kh94 Université Joseph Fourier - Grenoble 1 UJF 2015-12-31

BP 53 - 38041 Grenoble Cedex 9

http://www.ujf-grenoble.fr/ 026388804 https://ror.org/05sbt2524 Institut polytechnique de Grenoble - Grenoble Institute of Technology Grenoble INP 2007-01-01 2019-12-31

46 avenue Félix Viallet 38031 Grenoble Cedex 1

http://www.grenoble-inp.fr/