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Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC

Abstract : Nowadays a lot of complex circuits as SiP and SoC contain several ADCs and DACs in one package. The performances and number of these converters are continuously increasing, leading to ever higher test costs. This paper presents an experimental validation of a new concept called "Analogue Network of Converters" that permits to reduce drastically the testing time of these converters and requires only a low cost fully digital ATE.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00119266
Contributor : Serge Bernard <>
Submitted on : Friday, December 8, 2006 - 1:52:05 PM
Last modification on : Wednesday, August 28, 2019 - 7:12:02 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:42:14 PM

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  • HAL Id : lirmm-00119266, version 1

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Serge Bernard, Florence Azaïs, Philippe Cauvet, Mariane Comte, Vincent Kerzérho, et al.. Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC. IEEE International Mixed-Signal Testing Workshop, Jun 2006, Paris, France. pp.84-88. ⟨lirmm-00119266⟩

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