Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC
Abstract
Nowadays a lot of complex circuits as SiP and SoC contain several ADCs and DACs in one package. The performances and number of these converters are continuously increasing, leading to ever higher test costs. This paper presents an experimental validation of a new concept called "Analogue Network of Converters" that permits to reduce drastically the testing time of these converters and requires only a low cost fully digital ATE.
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