Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC

Abstract : Nowadays a lot of complex circuits as SiP and SoC contain several ADCs and DACs in one package. The performances and number of these converters are continuously increasing, leading to ever higher test costs. This paper presents an experimental validation of a new concept called "Analogue Network of Converters" that permits to reduce drastically the testing time of these converters and requires only a low cost fully digital ATE.
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Communication dans un congrès
IEEE International Mixed-Signal Testing Workshop, Jun 2006, Paris, France. pp.84-88, 2006
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Contributeur : Serge Bernard <>
Soumis le : vendredi 8 décembre 2006 - 13:52:05
Dernière modification le : vendredi 20 juillet 2018 - 12:34:01
Document(s) archivé(s) le : mardi 6 avril 2010 - 20:42:14

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Serge Bernard, Florence Azaïs, Philippe Cauvet, Mariane Comte, Vincent Kerzérho, et al.. Experimental Validation of the "Analogue Network of Converters" Technique to Test Complex SiP/SoC. IEEE International Mixed-Signal Testing Workshop, Jun 2006, Paris, France. pp.84-88, 2006. 〈lirmm-00119266〉

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