Reducing power dissipation during testing of complex integrated circuits (IC) or system-on-chip (SOC) has been acknowledged as a major concern. Similarly, minimising test power in embedded memories is important since they represent the main contributor to the overall IC power dissipation. In this paper we analyse the test power of SRAM memories and demonstrate that the normal pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this finding in order to minimise power dissipation during test by eliminating the unnecessary pre-charge activity. This is achieved through a modified pre-charge control circuitry. The efficiency of the proposed solution is validated through extensive Spice simulations.