In this paper we study the impact of leakage currents that strongly affect the operation of SRAM memories fabricated using nanoscale technologies. We show how the leakage currents, flowing through the pass transistors of unselected cells, may affect the read operation. A new fault model, named Leakage Read Fault (LRF), is introduced and the results of extensive Spice simulation on a 65nm SRAM are analyzed to evaluate the occurrence of the LRF for different operating conditions including supply voltage, temperature and frequency. Furthermore, the test requirements to cover LRFs are given and a low complexity (2N) March test is proposed for diagnostic purposes.