Statistical timing of digital integrated circuits, IEEE International Solid-State Circuits Conference, 2004. ,

Statistical timing analysis for intra-die process variations with spatial correlations, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), 2003. ,

DOI : 10.1109/ICCAD.2003.159781

STAC, Proceedings of the 41st annual conference on Design automation , DAC '04, 2004. ,

DOI : 10.1145/996566.996665

A general probabilistic framework for worst case timing analysis, pp.556-561, 2002. ,

Limitations of CMOS Supply-Voltage scaling by MOSFET threshold voltage variation, IEEE J. of Solid State Circuits, vol.30, pp.8947-949, 1995. ,

Low-Power CMOS Design, pp.0-7803, 1998. ,

DOI : 10.1109/9780470545058

Architecting voltage islands in core-based systemon-a-chip designs, inter. Symp. on Low power electronics and design, pp.180-185, 2004. ,

Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design , ISLPED '95, pp.3-8, 1995. ,

DOI : 10.1145/224081.224083

Physics of semiconductor devices [10] Changhae Park and alReversal of temperature dependence of integrated circuits operating at very low voltages, Proc. IEDM conference, pp.71-74, 1983. ,

Temperature Dependency in UDSM Process " Power and Timing Modeling, Optimization and Simulation, 15th Int, pp.693-703, 2005. ,

Transition time modeling in deep submicron CMOS, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21, issue.11, pp.1352-1363, 2002. ,

DOI : 10.1109/TCAD.2002.804088

URL : https://hal.archives-ouvertes.fr/lirmm-00239324

Continuous representation of the performance of a CMOS library, European Solid-State Circuits, ESSIRC'03 Conf, pp.595-598, 2003. ,

URL : https://hal.archives-ouvertes.fr/lirmm-00239459

Logical Effort Model Extension to Propagation Delay Representation " , accept for publication in the IEEE transaction on computer aided design ,

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid-State Circuits, vol.25, issue.2, pp.584-594, 1990. ,

DOI : 10.1109/4.52187

Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay, IEEE Journal of Solid-State Circuits, vol.29, issue.6, pp.646-654, 1994. ,

DOI : 10.1109/4.293109

Temperature effect on delay for low voltage applications, DATE, pp.680-685, 1998. ,

An investigation of MOSFET statistical and temperature effects, ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures, pp.202-207, 1992. ,

DOI : 10.1109/ICMTS.1992.185970

An extended Tanh law MOSFET model for high temperature circuit simulation, IEEE Journal of Solid-State Circuits, vol.30, issue.2, pp.147-150, 1995. ,

DOI : 10.1109/4.341743