Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2007

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Abstract

In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more effective in terms of resistive defect detection than that of URRFs and we list the necessary test conditions to detect them.

Domains

Electronics
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Dates and versions

lirmm-00194254 , version 1 (06-12-2007)

Identifiers

Cite

Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan. Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. Journal of Electronic Testing: : Theory and Applications, 2007, 23 (3), pp.435-444. ⟨10.1007/s10836-007-5003-9⟩. ⟨lirmm-00194254⟩
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