P. Pavan, Flash memory cells-an overview, Proc. of the IEEE, pp.1248-1271, 1997.
DOI : 10.1109/5.622505

M. Mohammad and K. Saluja, Flash memory disturbances: modeling and test, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, pp.218-224, 2001.
DOI : 10.1109/VTS.2001.923442

M. Mohammad and K. Saluja, Simulating program disturb faults in flash memories using spice compatible electrical model, IEEE Transactions on Electron Devices, vol.50, issue.11, pp.2286-2291, 2003.
DOI : 10.1109/TED.2003.816546

Y. Horng, J. Huang, and T. Chang, A Realistic Fault Model for Flash Memories, Proc. of IEEE Asian Test Symposium, pp.274-281, 2000.

O. Ginez, J. Daga, M. Combe, P. Girard, C. Landrault et al., An Overview of Failure Mechanisms in Embedded Flash Memories, 24th IEEE VLSI Test Symposium, pp.108-113, 2006.
DOI : 10.1109/VTS.2006.19

URL : https://hal.archives-ouvertes.fr/lirmm-00102761

O. Ginez, Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window, 25th IEEE VLSI Test Symmposium (VTS'07), 2007.
DOI : 10.1109/VTS.2007.52

URL : https://hal.archives-ouvertes.fr/lirmm-00151034

O. Ginez, Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories Semiconductor Memories: Technology, Testing and Reliability, Proc. of IEEE European Test Symposium, 1997.

K. Itoh, VLSI Memory Chip Design, 2001.
DOI : 10.1007/978-3-662-04478-0

A. J. Van-de-goor, Testing Semiconductor Memories, Theory and Practice, 1998.

A. J. Van-de-goor and I. B. Tlili, March tests for word-oriented memories, Proceedings Design, Automation and Test in Europe, pp.501-506, 1998.
DOI : 10.1109/DATE.1998.655905

W. H. Kautz, Testing of Faults in Wiring Interconnects, IEEE Trans. Computers, vol.23, issue.4, pp.358-363, 1974.

M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, 1990.
DOI : 10.1109/9780470544389