A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM

Abstract : Aggressive scaling of transistors is often accompanied by an increase in variability of its intrinsic parameters. In this paper, we point out the importance of considering sensitivity performances due to process variations (P) and operating conditions (V and T) during design process. In fact, by doing so, this has approved to be efficient in reducing the design timing margin introduced by the traditional corner analysis method, best and worst cases. More precisely, we illustrate that the statistical sizing method along with the appropriate choice of a dummy bitline driver, which is an essential component in a self-timed SRAM design in a read operation, reduces the sensitivities due to process dispersions and improves the design read margin. The memory considered is a 256kb SRAM design in 90nm technology node.
Type de document :
Communication dans un congrès
IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan, China. pp.032-036, 2007
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00198383
Contributeur : Philippe Maurine <>
Soumis le : lundi 17 décembre 2007 - 11:07:35
Dernière modification le : mercredi 24 octobre 2018 - 09:02:05

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  • HAL Id : lirmm-00198383, version 1

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Michael Yap San Min, Philippe Maurine, Magali Bastian, Michel Robert. A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM. IEEE International Workshop on Memory Technology, Design and Testing, Dec 2007, Taipei, Taiwan, China. pp.032-036, 2007. 〈lirmm-00198383〉

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