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On the Use of LVTPNP in ESD Protection Structures

Abstract : In this paper, design aspects, protection capabilities and applications of Low-Voltage-Triggered bipolar PNP in comparison with grounded-gate NMOS protection are presented. Experimental results are obtained in an embedded 0.18 μm salicided CMOS process.
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Contributor : Florence Azais <>
Submitted on : Tuesday, December 18, 2007 - 4:47:40 PM
Last modification on : Thursday, May 24, 2018 - 3:59:24 PM


  • HAL Id : lirmm-00199246, version 1



Antoine Rivière, Philippe Coll, David Bernard, Pascal Nouet, Florence Azaïs. On the Use of LVTPNP in ESD Protection Structures. IEW'07: International Electrostatic Discharge Workshop, May 2007, Lake Tahoe, CA, United States. ⟨lirmm-00199246⟩



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