On the Use of LVTPNP in ESD Protection Structures

Abstract : In this paper, design aspects, protection capabilities and applications of Low-Voltage-Triggered bipolar PNP in comparison with grounded-gate NMOS protection are presented. Experimental results are obtained in an embedded 0.18 μm salicided CMOS process.
Type de document :
Communication dans un congrès
IEW'07: International Electrostatic Discharge Workshop, May 2007, Lake Tahoe, CA, United States. 2007
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00199246
Contributeur : Florence Azais <>
Soumis le : mardi 18 décembre 2007 - 16:47:40
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00199246, version 1

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Antoine Rivière, Philippe Coll, David Bernard, Pascal Nouet, Florence Azaïs. On the Use of LVTPNP in ESD Protection Structures. IEW'07: International Electrostatic Discharge Workshop, May 2007, Lake Tahoe, CA, United States. 2007. 〈lirmm-00199246〉

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