E. J. Nassif, D. J. Nowak, N. J. Pearson, and . Rohrer, High performance CMOS variability in the 65 nm regime and beyond, IBM Journal of Research and Development, vol.50, pp.433-449, 2006.

A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs, IEEE Transactions on Electron Devices, vol.50, issue.9, pp.1837-1852, 2003.
DOI : 10.1109/TED.2003.815862

K. A. Bowman, S. G. Duvall, and J. D. , Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol.37, issue.2, pp.183-190, 2002.
DOI : 10.1109/4.982424

J. Pineda-de-gyvez and R. Rodriguez-montanes, Threshold voltage Mismatch Fault Modelling, Proceedings of the 21st IEEE VLSI Test Symposium, p.145, 2003.

M. Eisele, J. Berthold, D. Schmitt-landsiedel, and R. Mahnkopf, The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.5, issue.4, 1997.
DOI : 10.1109/92.645062

C. S. Amin, N. Menezes, K. Killpack, F. Dartu, U. Choudhury et al., Statistical static timing analysis, Proceedings of the 42nd annual conference on Design automation , DAC '05, 2005.
DOI : 10.1145/1065579.1065751

C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan, First-order Incremental Block-based Statistical Timing Analysis, Proc. 2004 DAC, pp.331-336, 2004.
DOI : 10.1145/996566.996663
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.104.6246

J. Xiong, V. Zolotv, N. Venkateswaran, and C. Visweswariah, Criticality Computation in Parameterizd Statistical Timing, Proc.2006 DAC, pp.63-68, 2006.

V. Migairou, R. Wilson, S. Engels, N. Azemard, and P. Maurine, Evaluation des marges temporelles de conception, 2007.