A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Journal Articles Integration, the VLSI Journal Year : 1993

A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation

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Modeling and Simulation Micro and nanotechnologies/Microelectronics

Nadine Azemard  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239254

Submitted on : Tuesday, February 5, 2008-11:39:11 AM

Last modification on : Friday, March 24, 2023-2:52:49 PM

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lirmm-00239254 , version 1 (05-02-2008)

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  • HAL Id : lirmm-00239254 , version 1

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Michel Robert, Guy Cathébras, Nadine Azemard, Denis Deschacht, Daniel Auvergne. A Performance Driven Layout Synthesis Approach for Digital CMOS Cell Implementation. Integration, the VLSI Journal, 1993. ⟨lirmm-00239254⟩

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