Short circuit power dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid State Circuits, pp.468-473, 1984. ,
Estimation of Short-Circuit Power Dissipation for Static CMOS Gates, IEICE Trans. Fundamentals, vol.3, 1996. ,
A novel macromodel for power estimation for CMOS structures, IEEE Trans. On CAD of integrated circuits ,
Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas, IEEE J. of Solid State Circuits, vol.25, 1990. ,
Propagation Delay and Short Circuit Power Dissipation Modeling of the CMOS Inverter, IEEE Trans. On Circuits And Systems-I: Fund. Theory And Applications, vol.45, 1998. ,
Computing The Entire Area/Power Comsumption Versus Delay Tradeoff Curve For Gate Sizing With A Piecewise Linear Simulator, IEEE Trans. On CAD onc. And Sys, vol.15, 1996. ,
An Exact Solution To The Transistor Sizing Problem For CMOS Circuits Using Convex Optimization, IEEE Trans. On CAD OfIntegrated Circuits And Systems, vol.12, 1993. ,
Transistor Sizing Power Consumption Of CMOS Circuits Under Delay Constraint, Int. Symp. On Low Power Design, vol.95, p.167 ,
Low-Power CMOS Digital Design, IEEE J. Of Solid State Circuits, vol.27, 1992. ,
Clustered voltage Scaling Technique for Low-Power Design, proc. of Int. Symp. on Low Power Design 95, pp.3-8 ,
Output transition time modeling of CMOS structures" To be published in Mai 2001 in the proc. of the IEEE Int, Symp. on Circuits And Systems ,
Internal power dissipation modeling and minimization for submicronic CMOS design, PATMOS, pp.531-536, 2000. ,
A Comprehensive Delay Macro-Model of Submicron CMOS Logic, IEEE J. of Solid States Circuits, vol.34, issue.1, pp.42-55, 1999. ,