Feasible delay Bound Definition - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Book Sections Year : 2002

Feasible delay Bound Definition

Abstract

Minimizing the number of iterations when satisfying performance constraints in IC design is of fundamental importance to limit the design iterations. We present a method to determine the feasibility of delay constraint imposed on circuit path. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinatorial paths. Then we characterise these bounds and present a method to determine, , the average weighted loading factor allowing to satisfy the delay constraint. Example of application is given on different ISCAS circuits.
Fichier principal
Vignette du fichier
Feasible_Delay_Bound_Definition.pdf (1.43 Mo) Télécharger le fichier
Origin : Publisher files allowed on an open archive
Loading...

Dates and versions

lirmm-00239363 , version 1 (11-09-2019)

Identifiers

Cite

Nadine Azemard, Michel Aline, Philippe Maurine, Daniel Auvergne. Feasible delay Bound Definition. SOC Design Methodologies, 90, Kluwer Academic Publishers, pp.325-335, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_40⟩. ⟨lirmm-00239363⟩
152 View
69 Download

Altmetric

Share

Gmail Facebook X LinkedIn More