Power vs Delay in Gate Sizing: Conflicting Objectives, Proceeding of the IEEFJACM ICCAD, pp.463-466, 1995. ,
Critical Path Selection for Performance Optimization, IEEE trans. On CAD of Integrated Circuits and Systems, vol.12, pp.185-195, 1995. ,
Local Gate Resizing for Critical Path Optimization" DCIS'99, Palma de Majorqua, Espagne, pp.16-19, 1999. ,
High Level Power Modeling, Estimation and Optimization, IEEE trans. on CAD of Integrated Circuits and Systems, vol.17, pp.1061-1079, 1998. ,
Fanout Optimization using a gain-based Delay model, 1999. ,
A new algorithm for minimizing Convex Functions Over Convex sets, proceedings oflEEE Foundations of Computer Science, pp.332-337, 1989. ,
Computing the Entire Active Area/Power Consumption versus Delay Tradeoff Curve for Gate Sizing with a Piecewise Linear Simulator, IEEE trans. on CAD of Integrated Circuits and Systems, vo1.l5, pp.1424-1434, 1996. ,
Designing for Speed on the Back of an Envelops, Advanced Research in VLSI, 1991. ,
An exact solution to the transistor sizing problem for CMOS circuits using convex functions, IEEE trans. CAD, pp.1621-1634, 1993. ,
On the Global Fanout Optimization Problem, IWLS, 1999. ,
The Fanout Problem: From Theory to Practice, Advanced Research in VLSI: Proceedings of the 1989 Decennial Caltech Conferences, pp.69-99, 1989. ,
Power Conscious CAD tools and Methodologies: a Perspective, Proc. IEEE, vo1.83, n04, pp.570-593, 1995. ,
A Novel Macromodel for power estimation in CMOS structures, IEEE trans. On CAD of Integrated Circuits and Systems, vol.17, pp.1090-1098, 1998. ,
Mixed Design of Integrated Circuits and Systems, 1998. ,
A virtual CMOS library approach for fast layout synthesis, VLSI'99, pp.415-426, 1999. ,
A comprehensive delay macromodeling for submicron CMOS logics, IEEE J. of Solid State Circuits, vol.34, pp.42-55, 1999. ,
Logical Effort: Designing Fast CMOS Circuits, 1999. ,
Output transition time modeling of CMOS structures" pp. V-363-V-366, ISCAS, vol.01 ,