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 Formal Sizing Rules of CMOS Circuits Daniel Auvergne 56484139d200b1bb8840e658c7cb5635 lirmm.fr 835730 171345-835730 Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr nadine-azemard 20666 32166-20666 https://www.idref.fr/068448813 Vincent Bonzom 285533-0 Denis Deschacht 20596418fd9e00395ddd6b18cef2bad7 lirmm.fr 938483 699461-938483 Michel Robert 9c0d7463dc45ca4a00f86b4653d59e36 lirmm.fr michel-robert 938334 107144-938334 https://orcid.org/0000-0002-5075-2898 Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr 2022-03-19 10:43:43 2023-03-24 14:53:26 2022-03-19 10:56:23 1991-02-25 2022-03-19 contributor Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr CCSD lirmm-00239374 https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239374 auvergne:lirmm-00239374 <i>EDAC 1991 - European Conference on Design Automation</i>, Feb 1991, Amsterdam, Netherlands. pp.96-100, <a target="_blank" href="https://dx.doi.org/10.1109/EDAC.1991.206368">&#x27E8;10.1109/EDAC.1991.206368&#x27E9;</a> EDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.96-100, &#x27E8;10.1109/EDAC.1991.206368&#x27E9; HAL Authorization CNRS - Centre national de la recherche scientifique SysMic Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Réseau de recherche en Théorie des Systèmes Distribués, Modélisation, Analyse et Contrôle des Systèmes MIC Département Microélectronique Mathématiques, Informatique, Physique et Systèmes Université de Montpellier Université de Montpellier (2015-2021) International No No Yes Yes Formal Sizing Rules of CMOS Circuits Daniel Auvergne 56484139d200b1bb8840e658c7cb5635 lirmm.fr 835730 171345-835730 Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr nadine-azemard 20666 32166-20666 https://www.idref.fr/068448813 Vincent Bonzom 285533-0 Denis Deschacht 20596418fd9e00395ddd6b18cef2bad7 lirmm.fr 938483 699461-938483 Michel Robert 9c0d7463dc45ca4a00f86b4653d59e36 lirmm.fr michel-robert 938334 107144-938334 https://orcid.org/0000-0002-5075-2898 Proceedings of the European Conference on Design Automation EDAC 1991 - European Conference on Design Automation 1991-02-25 1991-02-28 Amsterdam Netherlands 96-100 1991 10.1109/EDAC.1991.206368 English CMOS integrated circuits Computer Science [cs]/Modeling and Simulation Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Conference papers Conference papers Conference papers

Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.

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