Evaluation of VLSI Layout Implementation for Efficiency
Abstract
As an attempt to define a priori mapping rules for performance driven layout, the authors show in this paper how an automatic module generator can be used to compare different implementation styles of regular layout. Speed and area performances of gate and linear matrix approaches are compared. It is clearly shown that abutment of diffusions results in lower 'locox' parasitic capacitances inducing higher speed performances for linear matrix style.
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