Skip to Main content Skip to Navigation
Conference papers

Evaluation of VLSI Layout Implementation for Efficiency

Michel Robert 1 Joel Trauchessec 2 Guy Cathébras 3, 1 Vincent Bonzom 2 Nadine Azemard 1 Denis Deschacht 1 Daniel Auvergne 2 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 DEMAR - Artificial movement and gait restoration
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, CRISAM - Inria Sophia Antipolis - Méditerranée
Abstract : As an attempt to define a priori mapping rules for performance driven layout, the authors show in this paper how an automatic module generator can be used to compare different implementation styles of regular layout. Speed and area performances of gate and linear matrix approaches are compared. It is clearly shown that abutment of diffusions results in lower 'locox' parasitic capacitances inducing higher speed performances for linear matrix style.
Keywords : CMOS logic circuits
Complete list of metadata

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239384
Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Saturday, March 19, 2022 - 11:02:03 AM
Last modification on : Friday, August 5, 2022 - 10:48:24 AM
Long-term archiving on: : Monday, June 20, 2022 - 6:13:05 PM

File

robert1991.pdf
Files produced by the author(s)

Identifiers

Citation

Michel Robert, Joel Trauchessec, Guy Cathébras, Vincent Bonzom, Nadine Azemard, et al.. Evaluation of VLSI Layout Implementation for Efficiency. EURO-ASIC 1991 - European Conference on Design Automation with European Event in ASIC Design, May 1991, Paris, France. pp.362-365, ⟨10.1109/EUASIC.1991.212836⟩. ⟨lirmm-00239384⟩

Share

Metrics

Record views

268

Files downloads

7