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P.SIZE: A Sizing aid for Optimized Designs

Abstract : Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. The authors present the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239396
Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Saturday, March 19, 2022 - 11:18:29 AM
Last modification on : Friday, August 5, 2022 - 10:48:24 AM
Long-term archiving on: : Monday, June 20, 2022 - 6:13:03 PM

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Nadine Azemard, Vincent Bonzom, Daniel Auvergne. P.SIZE: A Sizing aid for Optimized Designs. EURODAC 1992 - European Design Automation Conference, Sep 1992, Hamburg, Germany. pp.160-166, ⟨10.1109/EURDAC.1992.246248⟩. ⟨lirmm-00239396⟩

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