An optimized output stage for Mos integrated circuits, IEEE J. Solid State circuits, vol.10, pp.106-109, 1975. ,
Comments on 'An optimized output stage for MOS integrated circuits', IEEE J. Solid State circuits, vol.10, pp.185-186, 1975. ,
Introduction to VLSI systems, 1980. ,
Principles of CMOS VLSI design, 1985. ,
CMOS circuit speed and buffer optimization, IEEE Trans. on CAD, vol.2, issue.6, pp.270-281, 1987. ,
CMOS tapered buffer, IEEE J. Solid State Circuits, vol.25, pp.1005-1008, 1990. ,
optimum tapered buffer, IEEE J. Solid State circuits, vol.27, pp.118-119, 1992. ,
A unified theory for mixed CMOS/BiCMOS buffer optimization, IEEE J. Solid State circuits, vol.27, pp.1014-1019, 1992. ,
short circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid State circuits, vol.19, pp.468-473, 1984. ,
Variable Taper CMOS buffer, IEEE J. of Solid State Circuits, vol.26, issue.9, pp.1265-1269, 1991. ,
Explicit formulation of delays on CMOS data path, IEEE J. of Solid State Circuits, vol.23, pp.1257-1264, 1988. ,
Energy control and accurate delay estimation in the design of CMOS buffers, IEEE J. of Solid State Circuits, vol.29, issue.9, pp.1150-1153, 1994. ,
TILOS: A polynomial programming approach to transistor sizing, Proc. ICCADnov, pp.326-328, 1985. ,
A module generator for optimized CMOS buffers" proc, 26th Design Automation Conference, pp.245-250, 1989. ,
iCOACH: a circuit optimization aid for CMOS high performance circuits, Integration the VLSI Journal, vol.10, pp.185-212, 1991. ,
Formal sizing rules of CMOS circuits, EDAC, European Design Automation Conference, pp.25-28, 1991. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00239374
design of tapered buffers with local interconnect capacitance, IEEE J. of Solid State Circuits, vol.30, pp.151-155, 1995. ,
Signal delay in RC tree networks, IEEE trans. on Computer Aided design, vol.6, pp.202-211, 1983. ,
Input waveform slope effects in CMOS delays, IEEE J. of Solid State Circuits, vol.25, issue.6, pp.1588-1590, 1990. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00239201
Process characterization with dynamic test structures, Electronics letters, vol.29, pp.1764-1766, 1993. ,
Explicit evaluation of short circuit power dissipation for CMOS logic structures, 1995's International Symposium on Low Power Design ,
URL : https://hal.archives-ouvertes.fr/lirmm-00241153
design of CMOS tapered buffer for minimum power delay product, IEEE J. of Solid State Circuits, vol.29, issue.9, pp.1142-1145 ,
Flexible macrocell layout generator, 4th ACM/SIGDA Physical design Workshop, pp.105-116, 1993. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00241344
Standard cell performance modeling, Proc. PATMOS, vol.94, pp.158-169, 1994. ,