Based on a path delay profiling tool we propose in this paper a method to determine the feasibility of delay constraint imposed on circuit path. From the evolution of the path delay profile with the transistor sizing conditions, we determine the upper and lower bounds for delay on critical paths. Using an explicit modeling of delay we characterize these bounds and present a method to determine, on the path under study, the average loading factor allowing to satisfy the delay constraint. Example of application is given on different ISCAS circuits.