HAL TEI export of lirmm-00239452 CCSD CC0 1.0 - Universal

HAL API Platform

 Timing Closure Management based on Delay Bound Determination Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr nadine-azemard 20666 32166-20666 https://www.idref.fr/068448813 Michel Aline 285524-0 Philippe Maurine 95c9402fd23112808a8f6dfbc6fe5eaf lirmm.fr philippe-maurine 22073 40706-22073 https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate https://www.idref.fr/144880717 https://orcid.org/0000-0002-9706-5710 https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr Daniel Auvergne 56484139d200b1bb8840e658c7cb5635 lirmm.fr 835730 171345-835730 Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr 2008-02-05 17:36:55 2023-03-24 14:52:49 2008-02-06 09:46:01 2001-12-03 contributor Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr CCSD lirmm-00239452 https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239452 azemard:lirmm-00239452 <i>VLSI-SoC: Very Large Scale Integration - System-on-Chip</i>, Dec 2001, Montpellier, France. pp.430-434 VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.430-434 CNRS - Centre national de la recherche scientifique SysMic Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Réseau de recherche en Théorie des Systèmes Distribués, Modélisation, Analyse et Contrôle des Systèmes MIC Département Microélectronique Mathématiques, Informatique, Physique et Systèmes Université de Montpellier Université de Montpellier (2015-2021) International No No Yes Yes Timing Closure Management based on Delay Bound Determination Nadine Azemard dc3948fef6fd0ab809b817260ae5c8b7 lirmm.fr nadine-azemard 20666 32166-20666 https://www.idref.fr/068448813 Michel Aline 285524-0 Philippe Maurine 95c9402fd23112808a8f6dfbc6fe5eaf lirmm.fr philippe-maurine 22073 40706-22073 https://scholar.google.fr/citations?hl=fr&user=VduRIsgAAAAJ&view_op=list_works&sortby=pubdate https://www.idref.fr/144880717 https://orcid.org/0000-0002-9706-5710 https://scholar.google.fr/citations?user=VduRIsgAAAAJ&hl=fr Daniel Auvergne 56484139d200b1bb8840e658c7cb5635 lirmm.fr 835730 171345-835730 IFIP International Conference on Very Large Scale Integration - The Global System On Chip Design & CAD Conference VLSI-SoC: Very Large Scale Integration - System-on-Chip 2001-12-03 2001-12-05 Montpellier France 430-434 2001 English Computer Science [cs]/Modeling and Simulation Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Conference papers Conference papers Conference papers

In this paper we present a method to determine the feasibility of delay constraint imposed on circuit path. This is of prime importance in minimizing the number of iterations when satisfying performance constraints in IC design. From a layout oriented study of the path delay distribution, we show how to obtain the upper and lower bounds of the delay of combinational paths. Then we characterize these bounds and present a method to determine, on the path under study, the average weighted loading factor which allows to satisfy the delay constraint. Example of application is given on different ISCAS circuits.

 Conception et Test de Systèmes MICroélectroniques SysMIC
http://www.lirmm.fr/recherche/equipes/sysmic 139590827 0000000405990488 199111950H https://ror.org/013yean28 Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier LIRMM 1995-01-01 2021-12-31
161 rue Ada - 34095 Montpellier
https://www.lirmm.fr 0000000120970141 https://ror.org/051escj72 Université de Montpellier UM 2021-12-31
163 rue Auguste Broussonnet - 34090 Montpellier
http://www.umontpellier.fr/ 02636817X 0000000122597504 https://ror.org/02feahw73 Centre National de la Recherche Scientifique CNRS 1939-10-19
https://www.cnrs.fr/