Gate Speed Improvement at Minimal Power Dissipation

Abstract : We introduce a new gate sizing rule for significantly improving the speed performance of static logic paths designed in submicron CMOS technology. This methodology is based on the definition of local gate sizing criterion. It is directly deduced from analytical models of the output transition time and of the short circuit power dissipation, which are validated on a 0.18 µm CMOS process. This sizing methodology is shown to offer a low power implementation alternative that can be used as an initial solution, prior to any logic path optimisation.
Type de document :
Communication dans un congrès
APPCAS'02: IEEE Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239453
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 17:42:47
Dernière modification le : mercredi 24 octobre 2018 - 09:02:05

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  • HAL Id : lirmm-00239453, version 1

Citation

Philippe Maurine, Xavier Michel, Nadine Azemard, Daniel Auvergne. Gate Speed Improvement at Minimal Power Dissipation. APPCAS'02: IEEE Asia-Pacific Conference on Circuits and Systems, Oct 2002, Denpasar, Bali, pp.278-282, 2002. 〈lirmm-00239453〉

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