Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier
Conference Papers Year : 1992

Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising

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Micro and nanotechnologies/Microelectronics

Nadine Azemard  : Connect in order to contact the contributor

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241327

Submitted on : Wednesday, February 6, 2008-11:13:11 AM

Last modification on : Friday, March 24, 2023-2:52:49 PM

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lirmm-00241327 , version 1 (06-02-2008)

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  • HAL Id : lirmm-00241327 , version 1

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Nadine Azemard, Denis Deschacht, Michel Robert, Daniel Auvergne. Application of Explicit Delay Time Modelling to CMOS Data Path Evaluation and Transistor Sising. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 1992, Paris, France. pp.102-108. ⟨lirmm-00241327⟩

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