This paper adresses the problem of satisfying delay/power constraints using a post layout iterative gate sizing. Path sizing procedure is defined with a realistic evaluation of gate delay and power and an accurate estimation of parasitic capacitances. This sizing protocol is validated on ISCAS'85 benchmarks, and implemented in a prototype for Performance Optimization by Path selection (POPS). The efficiency of this sizing heuristic is compared to an industrial optimization tool, AMPS (Synopsis).